1. Field of the Invention
The present invention relates to an analog-to-digital converter, and more particularly, to a time-interleaved analog-to-digital converter.
2. Description of the Related Art
Please refer to FIG. 1, which is a block diagram of a conventional time-interleaved analog-to-digital converter with four sub-ADCs module 100. The time-interleaved analog-to-digital converter with four sub-ADCs 100 comprises: four sample-and-hold circuits (not shown in FIG. 1) and four sub-analog-to-digital converters 112, 114, 116, and 118. In general, due to the variances of the manufacturing process, each of the sub-analog-to-digital converters 112, 114, 116, and 118 may have mismatches among them. And the mismatches among the converters 112, 114, 116, and 118 may influence the effective-number-of-bits (ENOB) of the time-interleaved A/D converter 100.